
`include "common_header.verilog"

//  *************************************************************************
//  File : pause_tmr
//  *************************************************************************
//  This program is controlled by a written license agreement.
//  Unauthorized Reproduction or Use is Expressly Prohibited. 
//  Copyright (c) 2009 MoreThanIP.com, Germany
//  Designed by : Daniel Koehler
//  info@morethanip.com
//  *************************************************************************
//               Ethernet MAC Core 
//  *************************************************************************
//  Description: A pause timer that is loaded with a quanta and decrements
//               then until zero when allowed. Indicates expiry.
//  Version    : $Id: pause_tmr.v,v 1.1 2009/03/31 11:15:08 dk Exp $
//  *************************************************************************
module pause_tmr (

   reset,
   clk,
   clk_ena,
   qtime,
   dec_ok,
   quanta_val,
   tload,
   twait);

input   reset;          //  Async Active High reset
input   clk;            //  Clock      
input   clk_ena;        //  Clock enable
input   qtime;          //  pulse when pause time of 1 quanta expired (512 bits)
input   dec_ok;         //  allow decrementing the timer
input   [15:0] quanta_val; //  Pause Quanta value to load
input   tload;          //  load timer with given val
output   twait;         //  wait for timer, it is non-zero
reg     twait; 
reg     [15:0] qcnt;    //  current counter
reg     qdec;           //  decrement counter

always @(posedge reset or posedge clk)
   begin : process_1
   if (reset == 1'b 1)
      begin
      qcnt <= {16{1'b 0}};	
      qdec <= 1'b 0;	
      twait <= 1'b 0;	
      end
   else
      begin
        //  ------------
        //  CLOCK enable
        //  ------------
      if (clk_ena == 1'b 1)
         begin

        //  create counter decrement pulse
        //  ------------------------------
         if (dec_ok == 1'b 1 & qtime == 1'b 1)
            begin
            qdec <= 1'b 1;	
            end
         else
            begin
            qdec <= 1'b 0;	
            end

        //  the counter
        //  -----------
         if (tload == 1'b 1)
            begin
                //  load the counter
            qcnt <= quanta_val;	
            end
         else if (qdec == 1'b 1 & qcnt != 16'h 0000 )
            begin
            qcnt <= qcnt - 16'h 0001;	
            end

        //  indicate counter expired
        //  ------------------------
         if (qcnt == 16'h 0000)
            begin
            twait <= 1'b 0;	
            end
         else
            begin
                //  counter not expired yet, continue waiting
            twait <= 1'b 1;	
            end
         end

      end

   end


endmodule // module pause_tmr
